Digital computer with optically interconnected multiprocessor arrangement

ABSTRACT

In a digital computer with multiprocessor arrangement, each processor is a highly integrated computer chip on a semiconductor basis connected to the other processors in the arrangement, which are of same design, via highly meshed management system composed of meshes and nodes for transmitting digital signals. Peripheral devices such as keyboards, memories, monitors, image sensors, speech analysis units, speech synthesis units as well as transmitters are connected to the computer. According to the invention, the management system is a beam waveguide network. Each node is associated with a processor to which it is coupled via an optical emitter and an optical receiver. The new types of chip interconnection which result and hence the high packing density of the chips and large number of cross-connections obtained are particularly advantageous. The computer network has a high functional density and the computer and peripherals are unaffected by electromagnetic influences.

BACKGROUND OF THE INVENTION

According to current know-how, computer-relevant signals can betransmitted both electrically and optically. In this respect thepossibility exists in principle of using both types of transmissionoutside and inside the computer chips. The development of optical chipsis being pursued at present, but has not reached anything like theadvanced state, in particular in miniaturization, already attained inthe case of electronic chips. Thus, there are both optical andelectronic components for computers, to construct circuits by the onetype of transmission or the other. In addition, there are so-calledoptronic components for the realization of transitions between circuitregions having a different type of transmission.

In the case of digital computers of the generic type, a plurality ofprocessor units are operated simultaneously, in order to increase thecomputer speed. Wherever this concerns computers with neural networks, amore or less pronounced adaptiveness of the computers can be achieved bythe simultaneous operation of many processors. The individual functionalunits, processors and storage devices have a high packing density in thecase of electronic chips. The space requirement of processors is reducedand thereby the length of the internal transmission paths is shortened.The high packing density is achieved by the individual electronicswitching elements arranged on a chip being miniaturized to an evergreater degree with the aid of electron-beam lithography. Considerablefunctional densities are already attainable with computer systems basedon such chips. Nevertheless, it can be foreseen that there are limits tothe development of purely electronic supercomputers. What is meant hereby "supercomputers" is adaptive computers, which are conceivable only inmultiprocessor arrangements in the form of neural networks, it beingpossible, according to the application, for the number of interactingprocessors to be, for example, in the tens of thousands, or even higherby orders of magnitude. Computer structures with such numbers ofindividual processors can no longer be realized by processors of aconventional type if acceptable hardware dimensions are to bemaintained. In US-Z Aerospace America/June 1988, page 40, column 2,lines 28 to 41, a computer is described which is based on VLSICtechnology (Very Large Scale Integrated Chip) and can execute 250,000processes and 5 million cross-connections. Here it is then also statedthat, depending on the application, some millions of cross-connectionsmay be far too few. For example, pattern recognition by means of anoptical recording member having a million optoelectrically activeindividual elements requires a number of cross-connections between theindividual units of the computer which goes into the billions. In orderto advance development in this direction, new ways of chip contactingwould have to be found, since the interconnection of such large numbersof processors is very restricted by current contacting technology. Withthis technology, the individual chips are connected to the rest of thecomputer circuit by solder connections usually arranged on the edges oftheir packages.

As far as producing supercomputers of the abovementioned type isconcerned, the electronic type of transmission offers the followingadvantage:

The possibilities of miniaturization can be fully utilized in chipproduction. In this case, component dimensions, for example conductortrack widths, of 0.01 μm can be realized.

However, on the other hand there are the following disadvantages:

The necessary high number of cross-connections outside the chips hindersthe development of supercomputers tremendously.

Like all such lines, electrical cross-connections are very sensitive toelectromagnetic interference fields.

The inductances and capacitances always present on electricaltransmission paths have the effect of considerably restricting thetransmission rate and the transmission band widths on these paths.

If one considers the feasibility of optical concepts for the realizationof supercomputers, the following disadvantage is encountered inparticular:

Optical chips previously realized or conceived do not have the highdegree of miniaturization such as that already achieved in the case ofelectronic chips.

However, the following is advantageous in the case of optical computerconcepts:

The transmission paths concerned are insensitive to electromagneticinterference fields.

Optical transmission paths have neither disturbing inductances norcapacitances.

The question of optical or electrical arises not only with respect tothe chips and their connections to one another but also with respect tothe peripherals of a computer, that is to say with respect to thescreens, keyboards, sensors, drive circuits and so on. In order to makethese devices as insensitive to electromagnetic influences as possible,they are usually shielded appropriately, it already being possible forthe data lines to be realized by optical waveguides. For protectionagainst interferences getting into the devices via the supply lines,further interference suppression measures are necessary. Correspondingsolutions are relatively complex, in particular owing to the shieldingand filter arrangements required.

OBJECTS OF THE INVENTION

Accordingly, the invention is based on the objective of designing acomputer of the generic type, and the peripheral devices interactingwith it, in such a way that the advantages of the optical type oftransmission are combined in it with the advantages of electronic signalprocessing in such a way that the computer and the peripheral devicesare distinguished by a substantial immunity to electromagneticinfluences, it being possible to realize the numbers ofcross-connections typical for supercomputers.

In this case, it is particularly advantageous that new ways of chipinterconnection are obtained, so that a high packing density of thechips and a great number of cross-connections is achieved; this resultsin a high functional density of the computer network with simultaneousimmunity of the computer and of the peripheral devices toelectromagnetic influences.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is represented by means of the drawing and explained ingreater detail in the description of an example. In the drawing:

FIG. 1 shows a block diagram of a supercomputer,

FIG. 2 shows a cross-section through a multilayered chip,

FIG. 3 shows a metallized coating,

FIG. 4 shows a light guide layer,

FIG. 5 shows a photocell layer,

FIG. 6 shows a chip with functional units,

FIG. 7 shows a top layer,

FIG. 8 shows a chip grouping,

FIG. 9 shows an energy supply for a chip structure,

FIG. 10 shows a coupling-in point,

FIG. 11 shows a display unit,

FIG. 12 shows a driving circuit for the display unit according to FIG.11,

FIG. 13 shows a key element,

FIG. 14 shows a wiring for a keyboard with key elements according toFIG. 13,

FIG. 15 shows a microphone with wiring,

FIG. 16 shows a voice output part,

FIG. 17 shows an image sensor,

FIG. 18 shows a mass store arrangement,

FIG. 19 shows a combined pressure/temperature sensor and

FIG. 20 shows a signal structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a block diagram of a computer according to the inventionwith a neural processor network 1, the following functional units beingconnected. An energy supply unit 2, a data input field 3, a display unit4, a magnetic mass store 5, an image sensor 6, a voice analysis unit 7and a voice synthesis unit 8. Furthermore, as shown, the energy supplyunit 2 is in connection with each of the units 3 to 8. The processornetwork 1 has several hundred thousand individual processor chips, whichwith one another form a highly meshed network. The lines shown in thediagram are designed as optical waveguides. All inputs and outputs ofthe individual functional units have optoelectronic transducersconnected to the optical waveguides. The energy lines coming from theenergy supply unit 2 are also designed as optical waveguides. On accountof the highly meshed neural network 1, this computer is adaptive to acertain extent and, apart from the usual logical operations, can alsoexecute such operations in pattern recognition. In this case, both anoptical pattern recognition and an acoustic pattern recognition can beimplemented. In the case of optical pattern recognition, the signalinput into the computer 1 is performed by the image sensor 6 and/or bythe mass storage 5. In the case of acoustic pattern recognition, thedata input is performed by the voice analysis unit 7, which interactswith a microphone 9. The voice output is performed by means of the voicesynthesis unit 8, to which a loudspeaker 10 is connected.

FIG. 2 diagrammatically shows a cross-section through an individualprocessor chip 11, as is used in the above processor network 1. Thischip contains a complete processor and forms the basis of the computercircuit. The chip specifically comprises a metallic carrier layer 12,which serves as electromagnetic shielding and on which the furtherlayers are arranged. Arranged on the layer 12 is a light guide layer 13,consisting of a low-loss material, such as silicate. Above the layer 13there is a photocell layer 14, for example consisting of crystallinesilicon, over which a circuit carrier layer 15 is arranged, which mayconsist for example of silicon or GaAs (gallium arsenide). Within thislayer 15 there is the circuit of the processor, produced by means ofhighly resolving methods, for example by means of electron-beamlithography. A top layer 16 forms the upper termination of the chip.This layer, like the carrier layer 12, consists of metal and containsdefined light guide tracks. Arranged between the layers 13 and 14, 14and 15 as well as 15 and 16 there is in each case an insulating layer,denoted by 13', 14' and 15', respectively, and comprising of SiO₂. Thesaid insulating layers go over into boundary layers 14", 15", the layers14 and 15 being electrically separated from a metallic boundary layer25.

FIG. 3 shows in plan view the region of the metallic carrier layer 12 inrelation to the surface of the chip. This region has the shape of aregular hexagon, so that the individual chips can be arranged on thecarrier layer 12 in a space-saving way. The interface between the layer12 and the layer 13 is designed in such a way that the light introducedinto the light guide layer 13 is reflected to the maximum extent and fedto the photocell layer.

FIG. 4 shows a plan view of the light guide layer 13. This layer too,like all other layers of the chip, is of hexagonal shape. This layerpasses on the multispectral light, introduced at high power density,multimodally into the photocell layer 14.

FIG. 5 shows a plan view of the photocell layer 14. This layer has aspecific number of photocells, so that when irradiated from the lightguide layer 13, the layer delivers an electric voltage which is 20 to30% higher than the voltage which is required for supplying the circuitarranged in the layer 15. Subsequently, an adequately great controlrange for reliable operation of the computer chip is obtained. Thephotocell layer 14 is separated from the circuit carrier layer 15 by aninsulating layer 14', comprising of SiO₂.

FIG. 6 shows a plan view of the circuit carrier layer 15. The individualfunctional units of the chip are built up on this layer. The figurespecifically shows the following units. A processor unit 17, a supplyunit 18, a programmable memory 19, a direct-access memory 20, a buscoder 21, a bus decoder 22, an optical emitter 23 as well as an opticalreceiver 24. The processor unit 17 may be configured as an 8-bit, 16-bitor 32-bit computer. The supply unit 18 is in connection with thephotocell layer 14 and receives its input voltage from there. For thispurpose, the insulating layer 14' has a corresponding verticalthroughplating. The supply unit 18 stabilizes the input voltage to apredetermined value and supplies all the functional units of the chipwith it via corresponding electrical conductor tracks. The functionalunits are highly integrated semiconductor circuits, which areinterconnected via an internal electrical computer bus. The plan viewalso shows an uninterruptedly encircling metallic boundary layer 25,which surrounds the entire circuit arranged on the chip. Together withthe metallic layers 12 and 16, this layer represents an extremelyeffective shielding against magnetic and electromagnetic influences. Thedata exchange with the other, further processor chips, grouped togetherin a great number in the neural network, and with the peripheral unitsis performed via the optical emitter 23 and via the receiver 24.Consequently, the processor is now connected to the outside world onlyvia optical transmission paths, as a result of which minimal sensitivityto electromagnetic interference fields is obtained.

FIG. 7 shows a plan view of the light guide layer 16 according to FIG.2. This likewise hexagonally designed layer has in its center an opticalnode 26. Six optical waveguides 27 enter this node in a star shape. Theoptical waveguides 27 comprise a polymeric material of predeterminedattenuation and are fitted in recessed tracks arranged within the layer16. The node 26 acts as an optical coupling element and brings thechip-side coder and decoder units 21, 20 into optical contact with theoptical waveguides 27 via the respective emitter 23 or receiver 24.

FIG. 8 shows a cutout of a processor network, comprising a plurality ofprocessor chips, which are joined to one another with optimumutilization of space on account of the hexagonal shape. The individualchips are in connection with one another via a network formed from theoptical waveguides 27. The guides 27 are embedded in the closed carrierlayer 16, which covers all the processor chips. The nodes 26 act both asactive star couplers and passive star couplers of the network. Onaccount of the hexagonal shape of the chips with the central arrangementof the nodes 26, the network forms triangular meshes with the nodes ascorner points, each node 26 being connected to six optical waveguides27. This has the result, as a geometrical special case, that all thechip boundaries 28 are crossed at right angles by the optical waveguides27. By integration of a multiplicity of such chips with the layers 12,13 and 15, 16 described above, in each case a processor level is formed,which is combined with further such levels to form a block. In thisarrangement, optical throughplatings are provided at predeterminedpoints of the levels, so that the processor network is given a spatialdimension of extremely high functional density.

FIG. 9 shows the energy supply of a level 29, formed from the layers 12to 16, of the processor network with a controlled power supply 30, whichis in connection with a light source 33 via electrical lines 31, 32. Thechip structure described above is shown diagrammatically at bottom leftwithin the rectangular level 29. The top layer 16 with the opticalwaveguides 27 can be seen, as well as the shaded photocell layer 13, ina cutout form of representation. The light generated by the light source33 passes via a suitable optical waveguide 34 into the light guide layer13 of the processor level 29 and acts from there on the photocell layer13. In the photocell layer 13, an electric voltage is thereuponproduced, which serves for the electrical supply of the individualchips. An electric feed-back signal is derived from this voltage and fedvia a line 35 to the energy supply 30 as reference variable.

FIG. 10 shows a plan view of an optical node 26. This represents inpractice an arrangement of circular segment-shaped photodiodes 36, whichjointly cover over a closed circular area. The center 37 of the circleis left as a clearance for technical production reasons. The diodes 36are divided into two groups by a diametral parting line 38, to beprecise into emitting diodes 36a, 36b, 36c, . . . and receiving diodes,which are denoted by 36₁, 36₂, 36₃, . . . The individual emitting diodes36a, 36b, 36c, . . . operate on different wavelengths (colors), eachemitting diode being assigned a receiving diode, which operates at thesame wavelength. Seen topographically, the arrangement comprises aplurality of emitting diodes and receiving diodes of circularsegment-shaped outline in each case, the individual color segmentshaving a color-characteristic doping and being separately drivable bymeans of corresponding microelectronic lines. The light-emittingsurfaces of the diode arrangement are covered by a coupling element (notshown here), which establishes the optical connection between theindividual diodes 36 and the optical waveguides 27. By means of theseoptical nodes, each processor 11 can exchange data with the otherprocessors of the network by the combined color-division multiplex andtime-division multiplex method.

FIG. 11 shows a view of a display panel (display) 39, which is arrangedon a carrier plate 40. Arranged on this plate 40 are a multiplicity ofstrip-shaped, vertically running, individually drivable light-emittingdiodes (LEDs) B,G,R; B,G,R; B,G,R; . . ., of which only a few are shownhere. These diodes B,G,R, arranged in close succession, cover in a firstlayer the entire optically usable area of the display panel 39. Thereference symbols B,G,R in this case stand for blue, green, red. Theoverall width of such a triplet of diodes corresponds precisely to thewidth of one picture element. Over this first layer there lies in asecond layer a multiplicity of strip-shaped, horizontally arrangedliquid crystal (LCD) elements 41. These individually drivable elementsalso cover the entire visible surface of the display in closesuccession, the width of one element 41 corresponding precisely to theheight of one picture element. For protection of the arrangement, athird layer of a transparent material is provided, the surface of whichis designed in such a way that outside light impinging on it isreflected diffusely. The display 39 is completely blanked when all theLCD elements 41 are at the supply voltage. As in a cathode-ray picturetube, the image to be presented is composed of picture elements andlines, here too each line comprising a series of picture elements.However, in the case of the display shown, there is no pictureelement-related complicated dot-matrix wiring, as is necessary in thecase of directly displaying semiconductor displays. The blanking of therespective LCD line is deactivated by a deactivating pulse, so that thelight-emitting diodes lying behind become visible. As a result, a cutoutof the height of one picture line becomes transmissive for the LEDslying behind. A picture element is shown when precisely one tripletB,G,R of diodes is driven. The color and brightness of the pictureelement are governed in this case by the driving conditions. Anadvantage of this solution is that picture rolling is executed by meansof the LCD elements and the much faster line traversal is executed bymeans of the LED elements, better suited for this purpose. The build-upof such an image by picture elements and by lines, with driving of thecolor and brightness values, is taken over by a corresponding picturedrive.

FIG. 12 shows the display 39 according to FIG. 11 with the LEDs B,G,Rand the LCDs 41 with its outer wiring, comprising a display processor42, an LED column control 43, an LED column driver 44 and an LCD linecontrol 45 and an LCD line driver 46. A power supply 47, which is fed bya photovoltaic unit 48, serves for the energy supply of this circuit.This unit 48 converts light, which is radiated in, for instance from alight source, directly via the light energy carrier level, into anelectric voltage, which is stabilized by the power supply 47 and passedon to the electronic units 43 to 46. The driving of the displayprocessor 42 takes place from the processor network 1 via the opticalwaveguides 27. The processor 42 controls the picture elements runningoff per line with respect to brightness and color by means of the LEDcolumn control 43 and the column driver 44. The vertical driving of therespective LCD image line is carried out by the display processor 42 viathe LCD line control 45 and the line driver 46. In this arrangement, thecontrol signals concerned are raised to the required power level by therespective drivers. With this display it is possible to present colorimages running off in serial succession on a semiconductor flat screenat reduced information rate and constant image resolution in a simpleform, as in the case of color television.

FIG. 13 shows a section through a keyboard element 49 with a key 50 anda capsule 51 of a magnetically shielded material, in which there is acarrier material with a liquid crystal 52. Coupled to each side of thecrystal 52 is an optical waveguide 27. Above the liquid crystal 52 thereis a Hall generator 54, the electric outputs of which are connected tothe connections of the crystal 52. Arranged on the underside of the key50 is a shielding plate 56, which carries a permanent magnet 53. Betweenthe permanent magnet 53 and the Hall generator 54, an air gap ismaintained by a spring. In the undepressed position of the key 50, theliquid crystal 52 is transparent, so that the luminous flux enteringfrom the left in the direction of the arrow can pass the keyboardelement 49 unhindered. If the key 50 is then depressed, the permanentmagnet 50 approaches the Hall generator 54, so that the latter emits avoltage to the liquid crystal 52. As a result, the liquid crystal 52 isblanked, so that the said luminous flux is interrupted. In order that aclear off/on characteristic is obtained, it is envisaged that athreshold voltage-dependent Hall generator element is used.Consequently, a purely optically operating keyboard element which can bedisturbed neither by magnetic influences nor by electromagneticinfluences is obtained.

FIG. 14 shows a circuit of an input keyboard 57, based on the keyboardelements 49, with an input panel 66, on which the individual keys 50 arearranged. The energy supply of the circuit is performed via an opticalwaveguide 58, to which both the input panel 66 and a photocell layer 62are connected. The input panel 66 is connected via optical waveguides 59to a keyboard decoder and bus coder 60. The signals delivered by the buscoder 60 pass through a modulator 63 and a light emitter 64, which is inconnection with an optical waveguide 65. The voltage delivered by thephotocell layer 62 is fed to an energy supply 61, which supplies theunits 60, 63 and 64 with a controlled operating voltage. In the restposition of the keys 50, a maintained light signal appears on all theoptical waveguides 59. If, however, a key 50 is hit, the opticalwaveguide 59 controlled by this key 50 passes a blanking pulse on to thekeyboard decoder 60, which thereupon generates an electric digitalsignal corresponding to the character of the hit key 50 and passes it onto the modulator 63, which for its part is connected to the lightemitter 64. The active part of this emitter 64 is formed by a laserdiode, which sends its output signal to the processor network 1described above. The units shown are arranged inside the keyboardhousing. A corresponding flexible connecting cable contains both theoptical waveguide 65 for the signals to be transmitted and the opticalwaveguide 58 for the energy supply. There are no electrical leads.Consequently, this circuit too can be influenced neither by electricalinterferences nor by electromagnetic interferences.

FIG. 15 shows a microphone 66 for the input of voice signals into acomputer network, the generation and transmission of the signalsconcerned again being performed largely by optical means. A photocelllayer 67 is in connection via electrical lines with an energy supply 68,which for its part is connected to a laser diode 69. Between the laserdiode 69 and a receiving diode 71 there is a light-conducting membrane70 clamped in such a way that, in its position of rest, light ofconstant intensity falls on the diode 71. The voltage emitted by thediode 71 is fed to a demodulator 72. The signal delivered by thedemodulator 72 passes via an amplifier 73 to the input of a frequencyanalyzer 74 and thereafter runs through the following functional units;a coding unit 75, a modulator 76 and an emitting diode 77. When anacoustic signal 78 impinges on the membrane 70, the latter vibratesaccordingly, whereby the light refraction index of the membrane 70 isaltered analogously to this signal. As a result, the light transmittanceof the membrane 70 in the direction of the arrow 79 changes, so that theluminous flux flowing through the membrane 70 is also altered to thesame extent. Consequently, an electric voltage modulated by the acousticsignal appears at the output of the diode 71. This audio-frequencyvoltage is processed in the downstream functional units for input intothe computer circuit 1.

FIG. 16 shows a voice output part 80, essentially comprising an opticalreceiving diode 81, a decoder part 82, a voice generator 83, anamplifier 84, and a loudspeaker 85. Here too, an optronic energy supply,comprising a photocell layer 86 and a power supply unit 87, is provided.The computer circuit 1 (not shown here) is in connection with the voiceoutput part 80 via an optical waveguide 88. The functional units 81 to84 are, as described above, supplied with a controlled operating voltageby the power supply unit 87. If digitally modulated light signals thenreach the receiving diode 81 via the optical waveguide 88, said diodeconverts the light signal into a corresponding electric signal, which ispassed to the decoder 82. The latter only allows those signals to passwhich are intended for the voice generator 83, which then composes thewords to be reproduced from individual syllables. For this purpose, thevoice generator 83 has a syllable memory, contained in which there isfor each syllable encountered a characteristic set of commands, whichdetermines the generation of the audio-frequency signals concerned. Thefrequency spectra concerned are provided by an internal digital/analogconverter. Voice reproduction is then performed via the amplifier 84with the connected loudspeaker 85.

FIG. 17 shows an image sensor 89, serving to record moving color picturecontents, with a lens 90, a CCD matrix image sensor 91, and an imageprocessor 92, which is connected via an image coder 93 and a lightemitter 94 to an optical waveguide 95. Furthermore, the image processor92 is in connection via an image decoder 96 and a light receiver 97 withan optical waveguide 97. All the said functional units are realized byintegrated semiconductor circuits, for the energy supply of which aphotocell layer 99 and a power supply unit 100 are provided. The dataexchange with the computer unit 1 (not shown) is performed via theoptical waveguides 95 and 98. For energy supply, the photocell layer 99is connected via an energy optical waveguide to a correspondingcomputer-side light source.

FIG. 18 shows a mass store arrangement 101 with a writing reading anderasing unit 102, a writing reading erasing control 103 as well as amodulator coder 104 and a demodulator decoder 105, which are in eachcase connected via an optical transmitter 106 and receiver 107,respectively, via optical waveguides 108 and 109 to an optical data line110. The supply with operating voltage is again performed via a poweroptical waveguide, which feeds a power supply unit 113 via a photocelllayer 112. This unit supplies both the functional units 103 to 107designed as integrated semiconductor circuits and a drive motor 115,which is preceded by a motor control 114. The actual storage element isformed by a cylindrical storage rotor 116, provided on the outside witha data carrier layer. The coating of the rotor 116 is distinguished inthat data stored thereupon can be written and read optically and can beerased magnetically. The cylinder 116 is mounted in a concentricallyrotatable manner inside the writing reading erasing unit 102, likewisedesigned as a cylinder. Detail B shows in a lateral projection theconcentric arrangement of the cylinders 102 and 116. The non-rotatingcylinder 102 carries on its inner side a multiplicity of writing lasers117, reading diodes 118 and erasing heads 119, which are arranged lyingdirectly opposite the data carrier layer. These optronic orelectromagnetic elements 117 to 119 are arranged in microminiaturizedform in an area-covering manner on a flexible foil, which is fastened onthe inner side of the cylinder 102. Due to the rotational movement ofthe storage cylinder 116 and the closely compact arrangement of theaccess elements (writing laser 117, reading diodes 118) in the axialdirection, a very large number of data tracks are defined on thecircumferential surface of the cylinder 116. Since the access elements116, 117 are arranged in a closely compact manner not only in the axialdirection but also in the circumferential direction, each data track isassigned a multiplicity of these elements. All the access elements 117,118 as well as the erasing heads 119 evenly distributed thereunder areconnected via the control 103 to the nodes of the processor network 1 inparallel connection. This design of a mass store has no moving partsapart from the cylinder 116 and the motor 115. When searching for aspecific stored data record, all the reading diodes 118 are activatedsimultaneously. This produces extremely short access times. Onlyfractions of a cylinder revolution elapse from a search command beingactivated to the data record concerned being located.

FIG. 19 shows a circuit of a combined measured-value transmitter 120with a piezo-pressure sensor 121 and a resistance-temperature sensor122. Both elements are connected via an analog to digital converter 123,a coder/decoder modulator 124 as well as an emitting diode 125 and areceiving diode 126 to an optical waveguide 127 in connection with theprocessor network. The units 123 to 126 designed as integratedsemiconductor circuits receive their operating voltage from a powersupply unit 128, which is fed by an energy optical waveguide 129 via aphotocell layer 130. The pressure sensor 121 delivers an electricvoltage proportional to the pressure detected to the A/D converter 123,which thereupon generates in a known way a digital signal correspondingto the voltage applied and introduces it into the optical waveguide 127via the further units 124 to 126. The temperature sensor 122 forms withthree resistors 131, 132, 133 an electric bridge circuit supplied by thepower supply unit 128, the outgoing line of which circuit is connectedto a further input of the converter 123. The operating principle of theoptronic data transmission used in this case is explained in greaterdetail below.

FIG. 20 shows the structure of the signals transmitted within theprocessor network. In principle, three types of information aretransmitted, namely the processor function addresses, the data priorityinformation and the data content information. The data contentinformation is divided into the data address and the data contentitself. The entire data traffic within the multiprocessor network ishandled with these three types of information.

The processor function addresses are necessary to allow the parallelprocessing of certain areas of activity ordered in self-organized formin the neural network. For this purpose, certain so-called mainprocessor areas are defined, which are in each case assigned to specificactivity areas. One such area of activity is, for example, theprocessing of data input by means of the keyboard. For example, witheach data input via the keyboard, six specific processors are addressedas primarily assigned processors by their processor function address inthe form of a fixed color-division multiplex code. These processorsthereby check in a selection of five out of six whether the followingdata are correctly transmitted. If a processor deviates with its testresult from the result of the other five, it is switched off as faulty.The remaining processors continue testing by the same procedure andappoint a neighboring standard processor as the main processor, whichnow takes over the tasks of the switched-off processor.

The data priority information represents a further importanttransmission parameter, since it indicates the degree of importance,that is to say the priority, of an item of information. A distinction isinitially drawn between data of high priority and data of low priority.Data of high priority are sent directly at 50% of the color carrieramplitude without base carrier component. Data of low priority aremodulated to 50% of constant color carrier amplitude. This measureachieves the effect that highly modulated signals 134, that is to saythe signals of high priority, experience priority treatment by thedecoder circuits of the neural network.

The data content information comprises two parts, namely a specific dataaddress as well as the actual data to be transmitted. In this case, eachpart forms a digital data message of specific bit length.

The three types of data mentioned above represent the basis of theoverall, self-organizing data transmission inside and outside the neuralnetwork, the operating principle of which is explained as follows. Forthis computer there is no superordinated overall running program,instead data processing and data management are executed according toprocedure patterns organized by the computer itself. Each individualprocessor has its own operating system, which enables it to carry outthe internal program run organization and organize the externalcommunication with the other processors. The respective processor-ownoperating system is stored in a corresponding EEPROM.

In order to avoid data collisions on the optical data bus network, aftereach information cycle, comprising the transmissions of the processorfunction address, the priority information, and the data contentinformation, all the processors are switched to reception again. If amain processor area has information of data priority 1, it initiallysends its processor function address into the bus network and starts thelatter with a single-color carrier signal, which immediately applies astransmit-blocking signal for all other main processors. In order thatall the processors operating on priority level 1 receive access to thedata bus, this so-called key signal is assigned cyclically to all themain processors. After one complete cycle, the bus is cleared for thedata traffic of priority level 2. This operates by the same procedurebut, after the termination of its cycle, if there are priority data oflevel 1, can wait again for a free priority gap. However, in order notto have to wait endlessly in the event of considerable data of prioritylevel 1 occurring, after the third cycle for level 1 a free cycle forlevel 2 is fixed. The various data content information is therebytransmitted by the parallel method via all the color carriers available.Consequently, a maximum throughput rate via the bus network is ensured.

If at this stage more complex tasks, such as those of patternrecognition, for example of voice analysis, are carried out, initiallythe area specified for this task as described above is addressed by mainprocessors. These then keep switching freely available standardprocessors on into task mode until their number is adequate formeaningful real-time processing in parallel operation. In this case, forexample, predetermined images or patterns are segmented in parallel andinitially taken over in the free RAMs of the main and standardprocessors, which then for their part address segment sectors and tracksassigned to them on the optomagnetic mass store by means of thecommunication procedure described above. Here, the processed patternsequences are stored permanently. If, within a learning process, thecomputer can remember a certain image pattern sequence by comparisonwith a predetermined pattern sequence, it compares per processor thepattern segment located in the mass store with the segment located inthe RAM. Deviations can consequently be recognized as erroneous andeliminated.

A refinement of the invention which is not shown consists in that theprocessor chip 11 is of square or rectangular shape.

A further refinement of the invention which is not shown consists inthat the storage cylinder 116 is provided on the outside and inside witha data carrier layer.

I claim:
 1. Digital computer having a plurality of processors, theprocessors being connected by means of optical waveguides for thetransmission of signals, said optical waveguides being connected to forman optical waveguide network, each node of the optical waveguide networkbeing assigned at least one processor chip which is coupled to the nodevia an optical emitter and an optical receiver in such a way that aninformation exchange between the processor chip assigned to the node andthe optical waveguide network is performed via the respective opticalnode, each said processor chip being electromagnetically shielded on allsides, each said processor chip being supplied the energy required foroperation via photocells arranged outside the metallic shielding, aslight energy via a light guide layer in such a way that, in energyconsumption and communication, there is no direct electrical connectionbetween the energy sources and the processor chips on the one hand andthe optical waveguide network and the processor chips on the other hand.2. The digital computer according to claim 1, further includingphotovoltaic converter, assigned to each processor chip, for theconversion of incident light into an electric voltage serving for thepower supply of the processor chip, with said processor chip having alight guide layer of an optically transparent material and a photocelllayer.
 3. The digital computer according to claim 1, wherein saidoptical node has a multiplicity of receiving diodes and emitting diodeswhich operate in pairs at the same color frequency.
 4. The digitalcomputer according to claim 1, in which each processor chip has ahexagonal outline shape, and wherein a multiplicity of processor chipsare combined in an interlocking manner to form a processor level, thechip boundaries being formed by the metallic boundary layer.
 5. Thedigital computer according to claim 1, wherein the meshes of the lightguide network have the shape of equilateral triangles.
 6. The digitalcomputer according to claim 4, wherein a multiplicity of said processorlevels are combined to form a block with optical data paths between theindividual processor levels existing at suitable points.
 7. The digitalcomputer according to claim 1, wherein the digital computer isinterfaced to a peripheral device and wherein a photocell layer isprovided for energy supply, which is in connection with an energy lightguide.